The DMP Programmer's Manual
The Digital Motion Processor in the InvenSense MPU-6050 family (MPU-6050, MPU-6500, MPU-9150, MPU-9250) and, as DMP3, in the ICM-20948: its architecture, memory, instruction set, host interface and assembly language.
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4. Instruction Set Summary
The tables list every instruction by class, with its length, its cycle count on each core and its
effect on F and R. Each mnemonic links to its definition in Chapter 5.
Reading the columns.
- Cycles count from the start of the instruction. “lane” gives the count under a 16-bit lane
mode. A dash means the core has no such instruction.
- F says what happens to the flag: “exact sign” is the sign of the result before it wraps, and
a dash means unchanged.
- R says what happens to the result register. “MPU: zeroed” applies only to the MPU-6050.
Clocks. The DMP clock on the parts measured is 8.199 MHz on the MPU-6050 (121.96 ns per cycle)
and 20.975 MHz on the ICM-20948 (47.68 ns per cycle). Another part differs by its oscillator’s
tolerance.
4.1 Arithmetic
| Mnemonic |
Operation |
Bytes |
Cycles MPU |
Cycles ICM |
F |
R |
add A,B[,inc] |
R := A + B; store or emit |
1 |
28, lane 22 |
26, lane 20 |
exact sign |
written |
rsub A,B[,inc] |
R := B − A; store or emit |
1 |
28, lane 22 |
26, lane 20 |
exact sign |
written |
mul A,B[,inc] |
R := A·B; store ⌊A·B / 2³⁰⌋ |
1 |
58, lane 52 |
25, lane 19 |
exact sign |
written |
nmul A,B[,inc] |
R := −A·B; store ⌊−A·B / 2³⁰⌋ |
1 |
58, lane 52 |
25, lane 19 |
exact sign |
written |
mac A,B[,inc] |
R := R + A·B; store ⌊R / 2³⁰⌋ |
1 |
60 |
27 |
sign of R |
accumulated |
macn A,B[,inc] |
R := R − A·B; store ⌊R / 2³⁰⌋ |
1 |
60 |
27 |
sign of R |
accumulated |
inc / inc.next |
M[P2] + 1 LSB of the lane, through the route |
1 |
23, lane 19 |
21, lane 17 |
exact sign |
written |
dec / dec.next |
M[P2] − 1 LSB of the lane, through the route |
1 |
23, lane 19 |
21, lane 17 |
exact sign |
written |
4.2 Logic and Compare
| Mnemonic |
Operation |
Bytes |
Cycles MPU |
Cycles ICM |
F |
R |
clamp A,B[,inc] |
A clamped to [−B, B]; store |
1 |
28, lane 22 |
26, lane 20 |
A was clamped |
the compare D |
cmp A,B |
F := A < 0 ≤ B; nothing stored |
1 |
17, lane 13 |
16, lane 12 |
sign test |
— |
and A,B[,inc] |
A AND B; store |
1 |
23, lane 17 |
22, lane 16 |
— |
— |
xor A,B[,inc] |
A XOR B; store |
1 |
23, lane 17 |
22, lane 16 |
— |
— |
test |
F := (R’s word == 0), at the lane |
1 |
5 |
4 |
R == 0 |
— |
cmp.eq / gt / lt / ne k,t (DMP3) |
F := (P1 word k & 0x3F) cond t |
3 |
— |
19 |
the compare |
— |
4.3 Data Transfer
4.4 Pointer Control
4.5 Routing and Predicates
| Mnemonic |
Operation |
Bytes |
Cycles MPU |
Cycles ICM |
F |
R |
store |
route := RAM |
1 |
5 |
4 |
— |
— |
fifo |
route := FIFO |
1 |
5 |
4 |
— |
— |
always |
disarm the predicate |
1 |
5 |
4 |
— |
— |
if f / if nf / if f.alt |
arm: run while F / while not F |
1 |
5 |
4 |
— |
— |
4.6 Modes and Program Flow
| Mnemonic |
Operation |
Bytes |
Cycles MPU |
Cycles ICM |
F |
R |
fmode m |
mode := m (m ≠ 4) |
1 |
5 |
4 |
— |
— |
mode4 (DMP3), nop.f4 (MPU) |
mode := 4; next byte ≥ 0x80 runs |
1 |
5 |
4 |
— |
— |
nop.f440 (MPU) |
mode := 4, nothing else |
2 |
10 |
— |
— |
— |
branch t (MPU) |
PC := PC + 2 + d; mode := 4 |
2 |
15 taken, 10 skipped |
— |
— |
— |
branch.m4 t (MPU) |
in mode 4: PC := PC + 1 + d |
1 |
10 taken, 5 skipped |
— |
— |
— |
jump t (DMP3) |
PC := t; mode := 4 |
3 |
— |
13 taken, 12 skipped |
— |
— |
jump.m4 t (DMP3) |
in mode 4: PC := t |
2 |
— |
9 |
— |
— |
call t (DMP3) |
push PC + 3; PC := t; mode := 4 |
3 |
— |
13 |
— |
— |
call.m4 t (DMP3) |
in mode 4: push PC + 2; PC := t |
2 |
— |
9 |
— |
— |
ret (DMP3) |
PC := pop |
1 |
— |
5 |
— |
— |
int (MPU) |
raise DMP_INT |
1 |
5 |
— |
— |
— |
int (DMP3) |
raise DMP_INT1 |
1 |
— |
4 |
— |
— |
int.f4 n (MPU) |
raise DMP_INT; mode := 4 |
2 |
10 |
— |
— |
— |
end |
end the pass |
1 |
— |
— |
— |
— |
4.7 Flags and the Result Register
| Instruction |
F |
R |
add, rsub, mul, nmul, inc, dec |
the sign of the exact result |
the exact result |
mac, macn |
the sign bit of R |
R ± A·B, modulo 2⁶⁴ |
clamp |
A was clamped |
the compare D |
cmp |
A < 0 ≤ B |
unchanged |
and, xor |
unchanged |
unchanged |
test |
R’s word, in the lane, is 0 |
unchanged |
cmp.eq … cmp.ne (DMP3) |
the comparison |
unchanged |
load, shl, sar (DMP3) |
unchanged |
the word stored |
mov, movx, clr, lo |
unchanged |
unchanged |
| a P2 move on the MPU-6050 |
unchanged |
0 |
| everything else |
unchanged |
unchanged |
While a predicate is armed, F does not change. The exceptions are test and the DMP3 compare,
which set it anyway.
4.8 Timing
- Start of a pass. The first instruction runs 110 cycles (MPU-6050) or 130 cycles (ICM-20948)
after the sample tick.
- Skipped instructions. An instruction a false predicate skips costs 5 cycles per byte on the
MPU-6050 and 4 on the ICM-20948.
- Branches. Bytes that a taken branch or jump passes over cost nothing.
- Sample writes. On the MPU-6050 each sample write that lands inside a running pass adds 14 to
28 cycles. The ICM-20948 adds nothing.
- Pass to pass. On the ICM-20948, when a tick is already pending, the next pass’s first
instruction comes about 150 cycles after
end.
Table 4-1. Instructions per sample period, after the start latency
| Sample rate |
Period |
MPU-6050: cycles |
ADDs |
MOVs |
ICM-20948: cycles |
ADDs |
MOVs |
| 1000 Hz |
1 ms |
8,089 |
288 |
449 |
20,845 |
801 |
1,226 |
| 500 Hz |
2 ms |
16,288 |
581 |
904 |
41,820 |
1,608 |
2,460 |
| 200 Hz |
5 ms |
40,885 |
1,460 |
2,271 |
104,745 |
4,028 |
6,161 |
| 100 Hz |
10 ms |
81,880 |
2,924 |
4,548 |
209,620 |
8,062 |
12,330 |
| 50 Hz |
20 ms |
163,870 |
5,852 |
9,103 |
419,370 |
16,129 |
24,668 |
A pass that does not fit its period delays the next one (§1.4). On the MPU-6050 the pass rate then
falls to the sample rate divided by a whole number.